Job Description
Minimum 6 years experience in ASICFPGA verification, including verification of complex ASICs at chiplevel Expertise in SystemVerilogUVM Knowledge of C andor Python preferred Networking protocol (i.e. Ethernet, OTN) andor FEC experience is a must Basic knowledge of SerDes and ADCDAC a plus Expertise in independently building SVUVM test benches Expertise in developing test cases and test plans Functional coverage, code coverage closure experience a must Gate sims and debugging. Experience in lab validation and bring up activities is a plus
💡 Quick Summary
Seeking a career-building opportunity? The Agasthya App Labs Senior Verification Design Engineer UVM position is now open for candidates interested in the Technician Jobs sector. This role in Ahmedabad offers a professional environment and growth potential.
Requirement Snapshot: Candidates should possess basic communication skills, a proactive attitude, and the ability to work in a team. Experience in Technician Jobs is a plus.