Job Description
Minimum qualifications:
• Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
• 2 years of experience with RTL design using Verilog/System Verilog and micro-architecture.
• Experience with ARM-based SoCs, interconnects, and ASIC methodology.
Preferred qualifications:
• Master’s degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
• 3 years of experience with IP design for clocking, interconnects, peripherals.
• Experience with methodologies for low-power estimation, timing closure, synthesis.
• Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC).
About The Job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
• Apply engineering best practices (e.g., code review, testing, refactoring) to the design and implementation of ASIC blocks.
• Write micro-architecture and own RTL implementation of key components and features.
• Engage with Verification and Silicon Validation teams to ensure functionality of design.
• Provide input on synthesis, timing closure, and Physical Design of digital blocks.
• Perform power, area, and performance trade-offs of digital designs and architectures.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, ****** orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
• Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
• 2 years of experience with RTL design using Verilog/System Verilog and micro-architecture.
• Experience with ARM-based SoCs, interconnects, and ASIC methodology.
Preferred qualifications:
• Master’s degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
• 3 years of experience with IP design for clocking, interconnects, peripherals.
• Experience with methodologies for low-power estimation, timing closure, synthesis.
• Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC).
About The Job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
• Apply engineering best practices (e.g., code review, testing, refactoring) to the design and implementation of ASIC blocks.
• Write micro-architecture and own RTL implementation of key components and features.
• Engage with Verification and Silicon Validation teams to ensure functionality of design.
• Provide input on synthesis, timing closure, and Physical Design of digital blocks.
• Perform power, area, and performance trade-offs of digital designs and architectures.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, ****** orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
💡 Quick Summary
Seeking a career-building opportunity? The ASIC AI|ML Design Engineer position is now open for candidates interested in the Mechanic Jobs sector. This role in Bangalore offers a professional environment and growth potential.
Requirement Snapshot: Candidates should possess basic communication skills, a proactive attitude, and the ability to work in a team. Experience in Mechanic Jobs is a plus.
