Job Description
The Foundation IP Corporate Memory Organization is looking for an experienced Memory Layout Designer to join its team.
Develop custom layout design for memory compilers (e.g., bit cells, SRAMs, Register Files). Perform detailed physical array planning, area optimization, critical wire analysis, and custom leaf cell layout.
Conduct complete layout verification including design rule compliance, electromigration, voltage drop (IR), selfheat, and other reliability checks.
May use custom autorouters and custom placers to efficiently construct layout. Provide feedback to circuit design engineers for new feature feasibility studies and implement circuit enhancement requests.
Develop and drive new and innovative layout methods to improve productivity and quality. Troubleshoot a wide variety of issues up to and including design and tool/flow/methodology issues used for layout design.
Qualifications
Hands-on experience with layouts of critical memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array, decoders, etc., in compiler context.
Solid experience with custom Memory (SRAM, RF, ROM) layout physical design Creates mask layouts of integrated circuits for a given specification and runs complete set of design verification tools for process design rules, electro migration, voltage drop (IR), ESD, and other reliability checks on the layouts.
Develops custom layout design memory compilers (e.g., bit cells, SRAMs, Register Files), performs area impact assessment with updated PDKs. Performs detailed physical array planning, power planning, area optimization, critical wire analysis, custom leaf cell layout.
Provides feedback to circuit design engineers for new feature feasibility studies and implements circuit enhancement requests. Knowledge of and experience with advanced FinFET processes in 5nm.
Solid experience using Cadence Virtuoso for custom layout physical design
Scripting knowledge/ SKILL coding is a plus.
Years of Experience: Bachelors with 3 to 6 yrs of experience.
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Develop custom layout design for memory compilers (e.g., bit cells, SRAMs, Register Files). Perform detailed physical array planning, area optimization, critical wire analysis, and custom leaf cell layout.
Conduct complete layout verification including design rule compliance, electromigration, voltage drop (IR), selfheat, and other reliability checks.
May use custom autorouters and custom placers to efficiently construct layout. Provide feedback to circuit design engineers for new feature feasibility studies and implement circuit enhancement requests.
Develop and drive new and innovative layout methods to improve productivity and quality. Troubleshoot a wide variety of issues up to and including design and tool/flow/methodology issues used for layout design.
Qualifications
Hands-on experience with layouts of critical memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array, decoders, etc., in compiler context.
Solid experience with custom Memory (SRAM, RF, ROM) layout physical design Creates mask layouts of integrated circuits for a given specification and runs complete set of design verification tools for process design rules, electro migration, voltage drop (IR), ESD, and other reliability checks on the layouts.
Develops custom layout design memory compilers (e.g., bit cells, SRAMs, Register Files), performs area impact assessment with updated PDKs. Performs detailed physical array planning, power planning, area optimization, critical wire analysis, custom leaf cell layout.
Provides feedback to circuit design engineers for new feature feasibility studies and implements circuit enhancement requests. Knowledge of and experience with advanced FinFET processes in 5nm.
Solid experience using Cadence Virtuoso for custom layout physical design
Scripting knowledge/ SKILL coding is a plus.
Years of Experience: Bachelors with 3 to 6 yrs of experience.
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
💡 Quick Summary
Seeking a career-building opportunity? The Layout Design Engineer position is now open for candidates interested in the Architect / Interior Designer Jobs sector. This role in India offers a professional environment and growth potential.
Requirement Snapshot: Candidates should possess basic communication skills, a proactive attitude, and the ability to work in a team. Experience in Architect / Interior Designer Jobs is a plus.
