Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.

As Microsoft's cloud business continues to grow, the ability to deploy new offerings and hardware infrastructure on time in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Cloud Compute Development Organization (CCDO) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

We are looking for an DDR digital design engineer with experience with DDR4/5 PHYs.

Responsibilities
• Integrate 3rd party DDR PHY design into 1st party DDR Memory Controller
• Interface with vendor
• Work closely with front end design and physical design teams to ensure correctness of the PHY design
• Implement any additional required functional units in Verilog
• Ensure high quality of the design from the perspectives of functionality, timing, CDC, RDC, LEC

Qualifications
• BS/MS in Electrical Engineering, Computer Engineering or Computer Science
• Some experience with DDR4 or DDR5 PHY
• Knowledge of the logic design flow including RTL coding, RTL simulation, synthesis, timing constraints, timing closure

Additional Preferred
• High speed digital design experience
• Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting, etc).
• Demonstrated proficiency in Computer Architecture, Digital Design, CPU/SoC design principles as part of CPU, SoC and/or IP development
• Demonstrated experience and knowledge of design clock crossings and power/UPF.
• Ability to write scripts using Perl, Tcl, Python etc.
• Experience in building and integrating any of the IPs such as memory controllers and DDR.
• Experience in building functional fabrics using Coherent and Non-Coherent protocols.
• Familiarity with Industry standard interface protocols such as AXI or CHI.
• Familiarity with Synthesis and STA tools.
• Good verbal and written communication skills.

#ahsi #SHPE24MSFT #SCHIE

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