Job Description
We are a well-funded product startup looking for RTL Design Engineers to contribute to the development of novel high performance AI accelerators from scratch. This role requires collaboration with cross-functional teams, including architect, software, verification, physical design, systems engineers, to define and implement next generation AI architectures.
Key Responsibilities:
• Design and implement high-performance TPUs/MPUs and other related AI blocks using RTL.
• Own IP/block-level RTL from spec to GDS, including design, synthesis, and timing closure.
• Optimize design for power, performance, and area (PPA).
• Interface with physical design and DFT (Design for Test) engineers for seamless integration.
• Drive design reviews, write design documentation, and support post silicon bring-up/debug.
Minimum Qualifications:
• B.S./M.S./Ph.D. in ECE/CS from top engineering college with 5-15 years of related experience.
• Previous experience in either high performance processor design or AI accelerator design is plus.
• Clear understanding of floating-point arithmetic, vector processing, SIMD, MIMD, VLIW, EPIC concepts.
• Strong grasp of digital design fundamentals, computer architecture, virtual memory and high-speed data-path design.
• Proficiency in Verilog/SystemVerilog and simulation tools.
• Experience with EDA tools (e.g., Synopsys, Cadence) for synthesis, lint, CDC, and timing analysis.
Key Responsibilities:
• Design and implement high-performance TPUs/MPUs and other related AI blocks using RTL.
• Own IP/block-level RTL from spec to GDS, including design, synthesis, and timing closure.
• Optimize design for power, performance, and area (PPA).
• Interface with physical design and DFT (Design for Test) engineers for seamless integration.
• Drive design reviews, write design documentation, and support post silicon bring-up/debug.
Minimum Qualifications:
• B.S./M.S./Ph.D. in ECE/CS from top engineering college with 5-15 years of related experience.
• Previous experience in either high performance processor design or AI accelerator design is plus.
• Clear understanding of floating-point arithmetic, vector processing, SIMD, MIMD, VLIW, EPIC concepts.
• Strong grasp of digital design fundamentals, computer architecture, virtual memory and high-speed data-path design.
• Proficiency in Verilog/SystemVerilog and simulation tools.
• Experience with EDA tools (e.g., Synopsys, Cadence) for synthesis, lint, CDC, and timing analysis.
💡 Quick Summary
Seeking a career-building opportunity? The NPrincipal IP/RTL Design Engineer position is now open for candidates interested in the Mechanic Jobs sector. This role in Jaipur offers a professional environment and growth potential.
Requirement Snapshot: Candidates should possess basic communication skills, a proactive attitude, and the ability to work in a team. Experience in Mechanic Jobs is a plus.
