Job Description
Job description
Sr. Engineer/Engineer – Physical Design
Job Title: Sr. Engineer/Engineer – Physical Design
We are looking for a highly skilled and experienced Physical Design Engineer to join our team.
The ideal candidate will have strong fundamentals in Physical design including Floorplan, power grid analysis, placement, cts, routing, DRC-LVS closure, timing closure, antenna fixing, signal integrity on 65nm, 45nm, 28nm, 16nm geometry.
Responsibilities:
• Floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing & signal integrity, Power grid analysis atc in ASIC PNR Flow
• Executing the block level place and route assignments from Netlist through GDS flow
• Full chip implementation of complex SoCs (RTL-to-GDSII)
• Closing STA timing across all corners and modes for blocks and generating ECO independently
• Working with design teams for closing CTS, IO timing, DFT timing
• Digital design automation, flow-automation and regression across RTL-to-GDSII
Requirements:
• Minimum 5 years experience in Physical Design
• Strong fundamentals on Physical design including Floorplan, power grid analysis, placement, cts, routing, DRC-LVS closure, timing closure, antenna fixing, signal integrity on 65nm, 45nm, 28nm, 16nm geometry
• Tcl, Perl, Shell scripting expertise
• Hands-on experience with Place and Route tools (Synopsys - ICC, Cadence – Innovus / Encounter)
• Experience on latest technology (28nm, 16nm, 7 nm)
Education Background:
• B.E./ B.S./ B.Tech/ M.S./ M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation Engineering
Sr. Engineer/Engineer – Physical Design
Job Title: Sr. Engineer/Engineer – Physical Design
We are looking for a highly skilled and experienced Physical Design Engineer to join our team.
The ideal candidate will have strong fundamentals in Physical design including Floorplan, power grid analysis, placement, cts, routing, DRC-LVS closure, timing closure, antenna fixing, signal integrity on 65nm, 45nm, 28nm, 16nm geometry.
Responsibilities:
• Floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing & signal integrity, Power grid analysis atc in ASIC PNR Flow
• Executing the block level place and route assignments from Netlist through GDS flow
• Full chip implementation of complex SoCs (RTL-to-GDSII)
• Closing STA timing across all corners and modes for blocks and generating ECO independently
• Working with design teams for closing CTS, IO timing, DFT timing
• Digital design automation, flow-automation and regression across RTL-to-GDSII
Requirements:
• Minimum 5 years experience in Physical Design
• Strong fundamentals on Physical design including Floorplan, power grid analysis, placement, cts, routing, DRC-LVS closure, timing closure, antenna fixing, signal integrity on 65nm, 45nm, 28nm, 16nm geometry
• Tcl, Perl, Shell scripting expertise
• Hands-on experience with Place and Route tools (Synopsys - ICC, Cadence – Innovus / Encounter)
• Experience on latest technology (28nm, 16nm, 7 nm)
Education Background:
• B.E./ B.S./ B.Tech/ M.S./ M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation Engineering
💡 Quick Summary
Seeking a career-building opportunity? The Physical Design Engineer position is now open for candidates interested in the Web / Graphic Design Jobs sector. This role in Alwar offers a professional environment and growth potential.
Requirement Snapshot: Candidates should possess basic communication skills, a proactive attitude, and the ability to work in a team. Experience in Web / Graphic Design Jobs is a plus.
