Senior Analog Layout Leads/Architects

We are actively looking to hire Senior Analog Layout Leads/Architects with (TSMC 5nm preferred) 7–15 years of experience to join our growing team.

📍 Locations: Hyderabad.

📅 Notice Period: 30 days or less preferred.

Job Description:

We’re seeking highly skilled professionals with a strong background in lower FINFET technology nodes (TSMC 5nm preferred) to contribute to cutting-edge analog layout design.

Key Skills & Requirements:

• Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization.

• Solid understanding of how layout impacts circuit performance (speed, area, etc.).

• Ability to implement layouts that meet tight design constraints and deliver high quality.

• Hands-on experience with CADENCE/SYNOPSYS layout tools and flows.

• Familiarity with scripting languages (PERL/SKILL) is a plus.

• Strong communication skills and experience working with cross-functional teams.

If this opportunity interests you—or if you know someone suitable—please send your updated resume to: 📧 maruthiprasad.e@eximietas.design.

Referrals are highly appreciated.

We look forward to connecting with talented engineers passionate about pushing the boundaries of analog layout design!

Maruthhi Naidu

Talent Associate - VLSI Manager

Eximietas Design - Visakhapatnam

maruthiprasad.e@eximietas.design

+91 8088969910.