Senior Embedded Engineer Lead Engineer PCI e UVM Verilog |4

Title of the Role : Senior Eng Tech leadJob Location : Blore, Pune, Ahmedabad ( all locations are priority)Relevant Exp Needed : 4 +yrsRole Requirements : Minimum 4 years of experience in System Verilog HVL. (not even 3.+yrs exp will work) Minimum 4 years of experience in UVM. Hands on experience of developing assertion, checkers, coverage and scenario creation. Must have executed at least 2 SoC Verification project. Experience in developing test and coverage plan, Verification environment and validation plan. The expertise of atleast one industry standard protocol like Ethernet, PCIe, MIPI, USB or similar is required. Expertise in IP as well as SOC verification Perl shell scripting is good to have. Verification candidate with 3 to 4 years of experience in System Verilog HVL and Protocol Exp. Atleast 1 or 2 projects with protocol exp (Ethernet, PCIe, MIPI, USB or similar is required) Executed 1 or 2 SOC projects or 1 2 IP projects.