Job Description
FPGA COE:
• The ASIC/FPGA Team works as Center of Excellence (COE) with all the business unit with teams around the globe, collaborating with them towards building prototypes, demonstrators, and new products enabling better innovation and business outcomes for Collins Aerospace.
• We work on advanced and disruptive technology, innovation, and methods relevant to multiple strategic business units (SBUs).
• We are seeking a highly motivated individual who is ready to perform the role of a Design Verification Lead Engineer as part of the ASIC/FPGA team.
Primary Responsibilities:
• Develop an effective suite of tests and test environments using system Verilog UVM, based tests to achieve predefined requirement verification goals.
• Experience in writing test-plan, self-checking testbenches to meet the verification criteria and code coverage.
• Protocols – PCIe, SPI, ARINC 42+, Mil 1553, Image processing.
• Actively participate in a team environment, working with verification, architecture, applications, and design teams to develop comprehensive verification plans and address issues.
• Verification environment development/update for block level and system level.
• Own and drive verification related activities, provide technical support, and proactively manage tasks to meet schedule goals.
• Verify structural and functional coverage of module and system level test suite.
• Advanced skills in various programming languages such as System Verilog/UVM, PERL or any scripting language.
• Apply techniques and skills required to identify a root cause of a given issue and very good debugging skills.
• Technical guidance to the junior engineers on verification tasks.
• The ASIC/FPGA Team works as Center of Excellence (COE) with all the business unit with teams around the globe, collaborating with them towards building prototypes, demonstrators, and new products enabling better innovation and business outcomes for Collins Aerospace.
• We work on advanced and disruptive technology, innovation, and methods relevant to multiple strategic business units (SBUs).
• We are seeking a highly motivated individual who is ready to perform the role of a Design Verification Lead Engineer as part of the ASIC/FPGA team.
Primary Responsibilities:
• Develop an effective suite of tests and test environments using system Verilog UVM, based tests to achieve predefined requirement verification goals.
• Experience in writing test-plan, self-checking testbenches to meet the verification criteria and code coverage.
• Protocols – PCIe, SPI, ARINC 42+, Mil 1553, Image processing.
• Actively participate in a team environment, working with verification, architecture, applications, and design teams to develop comprehensive verification plans and address issues.
• Verification environment development/update for block level and system level.
• Own and drive verification related activities, provide technical support, and proactively manage tasks to meet schedule goals.
• Verify structural and functional coverage of module and system level test suite.
• Advanced skills in various programming languages such as System Verilog/UVM, PERL or any scripting language.
• Apply techniques and skills required to identify a root cause of a given issue and very good debugging skills.
• Technical guidance to the junior engineers on verification tasks.
💡 Quick Summary
Seeking a career-building opportunity? The Senior Lead Engineer |Hybrid position is now open for candidates interested in the IT Engineer & Developer Jobs sector. This role in Bangalore offers a professional environment and growth potential.
Requirement Snapshot: Candidates should possess basic communication skills, a proactive attitude, and the ability to work in a team. Experience in IT Engineer & Developer Jobs is a plus.