Senior Verification Engineer Design Verification ASIC FPGA |4 10

Design Verification (Senior Verification Engineer)Location : Bangalore Pune AhmedabadExperience : 4 10 YearsAbout our Client :Is an Arrow company, is a leading global provider of product engineering and semiconductor design services. The company's service offerings include digital transformation and connected IoT solutions across various cloud platforms, including AWS and Azure.JOB REQUIREMENTS : Minimum 6 years experience in ASIC FPGA verification, including verification of complex ASICs at chip level Expertise in System Verilog UVM Knowledge of C and or Python preferred Networking protocol (i.e. Ethernet, OTN ) and or FEC experience is a must Basic knowledge of SerDes and ADC DAC a plus Expertise in independently building SV UVM test benches Expertise in developing test cases and test plans Functional coverage, code coverage closure experience a must Gate sims and debugging. Experience in lab validation and bring up activities is a plus Experience working of SV (System Verilog) and UVM (Universal Verification methodology) Experience of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB or similar is required. Must have executed at least 2 SoC Verification projects. At least 2 years of experience in handling team of 5 to 10 engineers.(FOR LEAD POSITION) In depth knowledge of design verification methodologies, such as OVM UVM, System Verilog, Assertion based formal verification as well as mixed signal co simulations, behavioural modelling etc. Good understanding of mixed signal system level considerations coupled with experience in digital design and verification of an SOCJob Benefit : One of the best company to work with< p>< p