Silicon Engineer, Digital Design, Quantum AI

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Mountain View, CA, USA; Goleta, CA, USA.
Minimum qualifications:
Bachelor's degree in electrical engineering or related technical field.
5 years of experience with digital logic design principles and RTL design concepts.
5 years of experience with IP Development or IP Integration.

Preferred qualifications:
8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
Experience building digital control and signal processing chains for mixed-signal sensing or actuation ASICs.
Experience with ASIC design methodologies for clock domain checks, reset checks, and low power design.
Experience in collaborating with system and hardware architecture, mixed-signal design, verification, physical design, software to build and deploy high-complexity ASICs to product.
Knowledge in at least one of these areas: CPU Processor Cores, Buses/Fabric/Network-on-a-Chip, Debug/Trace, Interrupts, or Clocks/Reset.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will be a vital member of the quantum electronics team, providing technical leadership in the area of ASIC digital design as we realize sophisticated electronics for control and readout of our future quantum computers. You will work as part of a team of digital, DV, PD, and RF/analog/mixed-signal engineers, collaborating with adjacent teams in the electronic, software, and quantum engineering areas to implement complex ASICs for use in the readout and control of our scaled quantum processors. You will work with quantum and hardware engineers to understand our quantum system and hardware requirements, translating them into silicon microarchitectures that implement desired functionality and performance.

You will directly own the development of RTL-based silicon solutions to deliver on these goals. You will interface closely to verification and physical design engineers to deliver robust, high-quality, and efficient designs. You will assist in the evaluation, selection, and integration of third-party IPs in order to build complex ASICs with minimal overhead. You will also contribute to planning and execution of post-silicon testing to validate the ASICs you help develop.
The full potential of quantum computing will be unlocked with a large-scale computer capable of complex, error-corrected computations. Google Quantum AI's mission is to build this computer and unlock solutions to classically intractable problems. Our roadmap is focused on advancing the capabilities of quantum computing and enabling meaningful applications.

The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
Participate in test plan and coverage analysis of the block and SOC-level verification and assist in debug and simulation to ensure bug-free design.
Work with a larger team of quantum researchers and other silicon engineers to contribute to architectural design of ASICs.
Develop high-performance, efficient silicon microarchitectures and deliver high-quality documentation and artifacts to empower colleagues to design or use these blocks.
Implement block-level and chip-level RTL with production-level quality (e.g., Lint/CDC/FV/UPF checks).
Participate in synthesis, timing/power closure, and silicon bring-up and evaluation, selection, and integration of vendor IPs for quantum control processors. Collaborate with external ASIC services partners to bring our designs to the product quickly and robustly.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, ****** orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
 

United States
California
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