System-on-Chip Design Engineer

Company Description

IntVerse.io provides integration services for businesses to connect and streamline their systems, data, and applications, enhancing efficiency and productivity. Our services are crucial for organizations relying on multiple systems and applications, ensuring seamless communication and collaboration across the business.

Role Description

This is a full-time on-site role for a System-on-Chip Design Engineer at IntVerse.io in Hyderabad. The System-on-Chip Design Engineer will be responsible for tasks related to Logic Design, Physical Design, Computer Architecture, RTL Design, and RTL Coding.

AMS DV:

EXP: 4+ yrs-—Lead is high priority

Must perform verification of complex designs and sub-systems using leading edge verification methodologies.

Must have a good understanding of analog circuit operation and its context in the AMS functional verification.

Must define requirements for analog modeling and drive model creation to make AMS functional verification efficient.

Must contribute to or influence the decisions on methodologies to be adopted for AMS functional verification.

Technically mentor and guide junior verification engineers.

Must have a good system level understanding of the IC use cases and devise test cases that emulate systems.

Architect the testbench and develop in UVM or Formal based verification approaches. Integrate the block testbench in chip-level UVM environment and verify integration.

JD 2:

IP DV

5+ years

Proficient in SV/ UVM based IP verification is a must.

Must have good debugging skills.

Should be able to understand the specification and come up with the Testplan and verification signoff criteria is a must.

Verification environment creation or testbench development experience is a must.

Experience in any of the complex protocols like USB, PCIe, Ethernet, DDR, Unipro, etc. is a big plus.

Experience with any of the slow-speed peripherals like I2C, SPI, or UART is a plus.

JD3:

SOC DV:

6 to 12 years of Experience in DV

Proficient in SoC verification is a must

Experience in creating a testplan for the blocks owned, testbench development and the delivery ownership is a must

Experience in ARM based CPU sub-system is a must. Experience in SMMU & GIC is desirable.

Experience in creating C lib functions & writing 'C' testcases for SoC DV is a must.

Experience in an SV/UVM-based environment and testcase writing is needed.

AXI and AHB experience are musts.

Experience in slow-speed peripherals is a must

Experience in writing and debugging complex datapaths is a must

Experience in debugging processor states for SoC verification is a plus.

JD4:

DFT Design:

· 5+ years to 10 yrs design experience

· Experience with owning chip level DFT and Post Silicon debug / analysis

· Understanding of DFT architectures like JTAG, Scan Compression Techniques (XOR, Adaptive, OP-MISR etc.), scan chain insertion and verification.

· Must have experience generating scan patterns and coverage statistics for various fault models like stuck at(Nominal and VBOX), IDDQ, Transition faults, JTAG BSDL, pattern generation for Memories(E-fuse etc.). Experience debugging tester failures of scan patterns, diagnosis and pattern re-generation.

· Understanding generation of functional patterns for ATE

· Knowledge of at least any one of an industry standard DFT tools (Cadence Modus, Synopsys Tetramax, Mentor Tessent Tools, etc)

· Design experience in MBIST / LBIST is an added advantage.

· Good understanding of constraints development for physical design implementation/static timing analysis.
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