Verification Engineer Synopsys SoC |3 15 yrs

Job Description : We need a Formal Verification Lead Manager who is hands on technical expert with excellent debugging skills in implementation issues and ability to come up with creative solutions. Own and manage complete team and provide technical leadership to the team during execution.Must Have Skills :1. Minimum Relevant experience is 3+ Years in System Verilog HVL SVA Assertions.2. Must have executed at least 2 3 SoC IP Formal Verification signoff projects.3. Must have used Synopsys VC Formal, Cadence Jasper or Questa Formal Tools comprehensively4. Hands on experience of developing Formal SV assertion checkers, coverage register, regressions.5. Functional Checks Assertions based Property coding to verify RTL Structures Data Path, Security, Register, Functional Safety and X Prorogation Verification6. Connectivity Checks on IP SoC connections Fault Analysis using Formal Testbench Analyzer Formal Coverage and Regressions.