Job description
Responsibilities:
• Module architecture and specification and helping with digital top architecture and specification.
• Development of RTL using Verilog/System Verilog and doing block-level testing before hand-off to verification.
• Synthesis of RTL and doing quality analysis of netlist - clock gating, power, gate count analysis, gate level simulations, LEC.
• Working with the verification team in helping develop and review test plans for blocks and full devices.
• Help with validation and bring-up related activities.
• Exp in Logic design, state machine.
• Exp in Project flow for digital, synthesis, net listing, and logic equivalence check.
• Ability to understand the block-level specifications and arrive at appropriate architecture and design to meet those specifications.

Requirements:
• Experience in the range of 2 to 5 years.
• Background in mixed-signal designs is a plus.
• A technology-related Bachelor's degree with related experience.
• Advanced system knowledge is preferable.
• Excellent written and verbal presentation skills.