Lead DFT Engineer

• *Lead DFT Engineer Role Summary**

We are seeking a highly skilled Lead DFT Engineer to drive the development of Digital Field Test (DFT) architectures, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional teams, and ensure world-class testability and manufacturability of silicon products.

Main Responsibilities:
• Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.
• Lead the implementation and verification of key DFT features, including scan insertion and compression, ATPG pattern generation, fault grading, MBIST, Logic BIST insertion, boundary scan, IJTAG, and end-to-end DFT flow management.
• Collaborate closely with RTL, STA, PD, and test engineering teams for seamless integration.
• Perform pattern generation, fault simulation, and debug test coverage gaps.
• Own DFT signoff, timing closure, and ATE pattern delivery.
• Support silicon bring-up, test vector validation on ATE, and yield optimization.
• Mentor and guide junior DFT engineers through design reviews and training sessions.
• Develop and maintain DFT automation scripts and infrastructure.

Requirements:
• Bachelor's or Master's degree in Electronics, Electrical Engineering, or VLSI Design.
• At least 7 years of experience in DFT for complex ASIC or SoC designs.
• Expertise in scan insertion, compression, ATPG, MBIST, boundary scan, and IJTAG.
• Hands-on experience with leading DFT tools, such as Synopsys DFT Compiler, TetraMAX, TestMAX, Siemens EDA Tessent ScanPro, and Cadence/others Modus and Encounter Test.
• Strong knowledge of RTL design, static timing analysis (STA), and synthesis flows.
• Proficiency in scripting languages like Python, Perl, and Tcl for flow automation.
• Deep understanding of silicon test challenges and test coverage improvement.
• Excellent leadership, team collaboration, and communication skills.

Preferred Qualifications:
• Experience with hierarchical DFT methodologies and low-power DFT techniques using UPF.
• Familiarity with post-silicon validation and failure analysis.
• Knowledge of safety-critical designs (ISO 26262) and functional safety.
• Experience working in advanced nodes, such as 7nm, 5nm, and FinFET