Job Description
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JSG, Inc. is currently looking for Verification Engineers who will help develop system level UVM test benches for various DDR5 DIMM products, Power Management IC (PMIC) and also CXL 2.0 products. Your contribution would be to lead and work with other global team members in building the infrastructure for system level SoC testing. You will also be responsible to functionally verify the system and IP components, using System Verilog and mixed signal verification techniques.
• Key Responsibilities:
• Knowledge of system level verification and PMIC IP verification;
• Be involved in silicon debug when necessary;
• Develop, drive and implement UVM System Verilog Testbench and infrastructure;
• Develop stimulus, coverage, SV assertions, scripts as necessary;
• Collaborate closely with component testing verification teams across our global sites;
• Interface with other engineering functions such as Design, Product, Spec Engineering;
• Debug regressions and failing simulations.
Qualifications:
• BS or MS in Electrical Engineering, Computer Engineering or equivalent;
• 7+ years of relevant work experience;
• Good understanding of CMOS circuit design;
• Strong understanding and hands on experience in building UVM Testbenches from scratch;
• Proficient with digital and analog simulation tools, e.g.: VCS, Xcellieum, Verdi etc.; Proficiency with OO language.
• Excellent debugging and problem solving skills;
• Strong understanding of DDR5 protocol or CXL 2.0 spec.
Salary range: $190 - $215K - Strong compensation package including bonuses!
Qualified/Interested candidates should apply immediately.
JSG, Inc. is currently looking for Verification Engineers who will help develop system level UVM test benches for various DDR5 DIMM products, Power Management IC (PMIC) and also CXL 2.0 products. Your contribution would be to lead and work with other global team members in building the infrastructure for system level SoC testing. You will also be responsible to functionally verify the system and IP components, using System Verilog and mixed signal verification techniques.
• Key Responsibilities:
• Knowledge of system level verification and PMIC IP verification;
• Be involved in silicon debug when necessary;
• Develop, drive and implement UVM System Verilog Testbench and infrastructure;
• Develop stimulus, coverage, SV assertions, scripts as necessary;
• Collaborate closely with component testing verification teams across our global sites;
• Interface with other engineering functions such as Design, Product, Spec Engineering;
• Debug regressions and failing simulations.
Qualifications:
• BS or MS in Electrical Engineering, Computer Engineering or equivalent;
• 7+ years of relevant work experience;
• Good understanding of CMOS circuit design;
• Strong understanding and hands on experience in building UVM Testbenches from scratch;
• Proficient with digital and analog simulation tools, e.g.: VCS, Xcellieum, Verdi etc.; Proficiency with OO language.
• Excellent debugging and problem solving skills;
• Strong understanding of DDR5 protocol or CXL 2.0 spec.
Salary range: $190 - $215K - Strong compensation package including bonuses!
Qualified/Interested candidates should apply immediately.
💡 Quick Summary
Seeking a career-building opportunity? The Sr. Verification Engineer (IC) position is now open for candidates interested in the Remote Jobs sector. This role in Atlanta offers a professional environment and growth potential.
Requirement Snapshot: Candidates should possess basic communication skills, a proactive attitude, and the ability to work in a team. Experience in Remote Jobs is a plus.