Job Description
K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.
The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.
With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we'd love for you to apply.
The Role
We are seeking a highly skilled Lead Digital ASIC Engineer to drive the design and implementation of digital subsystems for advanced wireless SoCs along with managing a team of ASIC design engineers. You will work as part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In this role, you will take ownership of significant digital blocks, lead technical initiatives, and contribute to the development of cutting-edge communication systems for space applications.
Responsibilities
• Lead and manage a team of digital design engineers, providing technical mentorship, career development, and performance management.
• Manage development schedules, track deliverables, and report status to senior leadership and cross-functional teams.
• Contribute to design and implementation of microarchitecture and RTL for key digital blocks in wireless SoCs, including DSP systems, interfaces, and control logic.
• Collaborate with system architects to translate high-level DSP algorithms and chip specifications into efficient hardware implementations.
• Develop RTL for complex digital subsystems such as filters, beamformers, FFT/IFFT engines, and digital front-ends.
• Contribute to design and integration of digital blocks for interfaces, power management, clocking, reset, test, and debug infrastructure.
• Work with analog/mixed-signal teams to define and implement digital-analog interfaces, calibration engines, and control logic.
• Optimize designs for power, performance, and area (PPA) while meeting timing, area, and power constraints.
• Collaborate with synthesis and backend teams to achieve timing closure and resolve design issues.
• Contribute to verification planning and work closely with verification teams to validate complex digital subsystems.
• Participate in chip bring-up and lab validation activities for digital subsystems.
• Support products through production and spaceflight operations.
• Mentor junior engineers and contribute to team technical growth and best practices.
Qualifications
• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of industry experience in digital ASIC design with ownership of complex digital blocks or subsystems.
• 3+ years of experience leading ASIC design teams or projects, including mentoring engineers and managing deliverables.
• Strong proficiency in RTL design using SystemVerilog or Verilog, with experience in synthesis and linting tools.
• Experience in microarchitecture definition and implementation based on architectural guidelines and analysis.
• Hands-on experience with timing closure, working effectively with synthesis and static timing analysis teams.
• Familiarity with DFT concepts and tools for scan and BIST insertion.
• Solid understanding of SoC design flows including clock/power domain crossing, timing constraints, and verification methodologies.
• Experience with DSP blocks for wireless communication systems (e.g., OFDM, MIMO, channel estimation, DFE).
• Proficiency with industry-standard EDA tools for design, synthesis, static timing analysis, and power analysis (e.g., Synopsys, Cadence, Siemens tools).
• Strong debugging, problem-solving, and communication skills with ability to work effectively in cross-functional teams.
Nice to Have
• Experience in wireless SoC development (e.g., cellular, Wi-Fi, satellite, or mmWave systems) with successful tapeouts.
• Design experience with datapath architectures, flow control, arbitration, FIFO, DMA, IOMMU, and SoC bus architectures.
• Experience with ARM's AXI/AHB bus architectures and protocols, and serial interfaces such as SPI, I3C, UART.
• Familiarity with DSP algorithm modeling using MATLAB, Python, or C++ and converting models into RTL implementations.
• Experience working with FEC, baseband PHYs, or digital beamforming architectures.
• Knowledge of digital calibration and control of RF/mixed-signal front ends.
• Exposure to hardware-software co-design and embedded processor integration.
• Experience working in fast-paced startup or cross-functional, geographically distributed teams.
Compensation and Benefits:
• Base salary range for this role is $200,000 – $300,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
If you don't meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!
If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.
Export Compliance
As defined in the ITAR, "U.S. Persons" include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a "U.S. Person."
The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a "U.S. person" as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.
Equal Opportunity
K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, ****** orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.
With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we'd love for you to apply.
The Role
We are seeking a highly skilled Lead Digital ASIC Engineer to drive the design and implementation of digital subsystems for advanced wireless SoCs along with managing a team of ASIC design engineers. You will work as part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In this role, you will take ownership of significant digital blocks, lead technical initiatives, and contribute to the development of cutting-edge communication systems for space applications.
Responsibilities
• Lead and manage a team of digital design engineers, providing technical mentorship, career development, and performance management.
• Manage development schedules, track deliverables, and report status to senior leadership and cross-functional teams.
• Contribute to design and implementation of microarchitecture and RTL for key digital blocks in wireless SoCs, including DSP systems, interfaces, and control logic.
• Collaborate with system architects to translate high-level DSP algorithms and chip specifications into efficient hardware implementations.
• Develop RTL for complex digital subsystems such as filters, beamformers, FFT/IFFT engines, and digital front-ends.
• Contribute to design and integration of digital blocks for interfaces, power management, clocking, reset, test, and debug infrastructure.
• Work with analog/mixed-signal teams to define and implement digital-analog interfaces, calibration engines, and control logic.
• Optimize designs for power, performance, and area (PPA) while meeting timing, area, and power constraints.
• Collaborate with synthesis and backend teams to achieve timing closure and resolve design issues.
• Contribute to verification planning and work closely with verification teams to validate complex digital subsystems.
• Participate in chip bring-up and lab validation activities for digital subsystems.
• Support products through production and spaceflight operations.
• Mentor junior engineers and contribute to team technical growth and best practices.
Qualifications
• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of industry experience in digital ASIC design with ownership of complex digital blocks or subsystems.
• 3+ years of experience leading ASIC design teams or projects, including mentoring engineers and managing deliverables.
• Strong proficiency in RTL design using SystemVerilog or Verilog, with experience in synthesis and linting tools.
• Experience in microarchitecture definition and implementation based on architectural guidelines and analysis.
• Hands-on experience with timing closure, working effectively with synthesis and static timing analysis teams.
• Familiarity with DFT concepts and tools for scan and BIST insertion.
• Solid understanding of SoC design flows including clock/power domain crossing, timing constraints, and verification methodologies.
• Experience with DSP blocks for wireless communication systems (e.g., OFDM, MIMO, channel estimation, DFE).
• Proficiency with industry-standard EDA tools for design, synthesis, static timing analysis, and power analysis (e.g., Synopsys, Cadence, Siemens tools).
• Strong debugging, problem-solving, and communication skills with ability to work effectively in cross-functional teams.
Nice to Have
• Experience in wireless SoC development (e.g., cellular, Wi-Fi, satellite, or mmWave systems) with successful tapeouts.
• Design experience with datapath architectures, flow control, arbitration, FIFO, DMA, IOMMU, and SoC bus architectures.
• Experience with ARM's AXI/AHB bus architectures and protocols, and serial interfaces such as SPI, I3C, UART.
• Familiarity with DSP algorithm modeling using MATLAB, Python, or C++ and converting models into RTL implementations.
• Experience working with FEC, baseband PHYs, or digital beamforming architectures.
• Knowledge of digital calibration and control of RF/mixed-signal front ends.
• Exposure to hardware-software co-design and embedded processor integration.
• Experience working in fast-paced startup or cross-functional, geographically distributed teams.
Compensation and Benefits:
• Base salary range for this role is $200,000 – $300,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
If you don't meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!
If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.
Export Compliance
As defined in the ITAR, "U.S. Persons" include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a "U.S. Person."
The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a "U.S. person" as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.
Equal Opportunity
K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, ****** orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
💡 Quick Summary
Seeking a career-building opportunity? The Lead Digital ASIC Design Engineer position is now open for candidates interested in the IT Engineer & Developer Jobs sector. This role in Los Alamos offers a professional environment and growth potential.
Requirement Snapshot: Candidates should possess basic communication skills, a proactive attitude, and the ability to work in a team. Experience in IT Engineer & Developer Jobs is a plus.
